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St. Joseph’s College of Engineering
E m p l o y a b i l i t y E n h a n c e m e n t C o u r s e o n R T L
Employability Enhancement Course on RTL
D e s i g n a n d V e r i f i c a t i o n
Design and Verification
The Department of Electronics & Communication
Engineering in collaboration with VLSI Design
Centre and TARAS SYSTEMS AND SOLUTIONS
recently hosted an Employability Enhancement
Course on RTL Design and Verification from
August 25 to September 2, 2025. Led by industry
experts Mr. Venkatesh Rajakutti and Ms.
Sabarisha, the program provided comprehensive
training on key aspects of VLSI design, including
digital fundamentals, RTL design with Verilog
HDL, and verification using SystemVerilog and
UVM architecture. This initiative equipped
participants with valuable skills essential for
careers in the VLSI industry.
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